C:/Computing/Processors-IO-Storage/ALU-CU-Registers/

The CPU (Central Processing Unit) gets input, and has to decide what to do with it

It interacts with its components, and produces an output based on that

The CU controls and coordinates all of the activities that the processor does

It directs data flow between the components

Coordinates the Fetch-Decode-Execute cycle

It sends memory Read-Write requests and various other signals

Uses status registers, and the system clock quite heavily

The PC holds the memory address of the next instruction

This could be the next address, such as 0x0001 coming after 0x0000 or it could be a jump, such as 0x1010 coming after 0x0001

A jump could be seen as a branch, like in an if (true) {} else {} statement

At the start of the Fetch-Decode-Execute cycle, the address held in the PC is copied to the MAR

The MAR holds the address of the memory location of the data or instruction to read or write from

It sends the addressed along the address bus

The MDR is used to hold the data to that has been read, or will be written to memory

Sometimes, it is known as the MBR and also often called the "gateway to the processor"

This is because all data must pass through the MDR while it is being read or written to

The CIR holds the current instruction being executed

Data from the MDR is copied into the CIR only if it is an instruction

Holds an op code, and an operand, such as LDA 1000 would load the data from memory address 8

The ALU does maths, and logic

It can do the following things:

• Add
• Subtract
• Multiply
• Divide
• Bitwise Shifts (left and right)
• Comparison: AND, OR, NOT, XOR

It often contains general purpose registers such as the Accumulator that holds results

The Accumulator is a general purpose register

The CPU uses this to hold the results of the calculations it performs

The results from the ALU are in this register

Busses come in two types: unidirectional, and bidirectional

There are three types:

Address Bus

Contains the address in memory

This is unidirectional, it goes only one way, from the processor to the Main Memory

Data Bus

This contains the actual data being transferred

This is bidirectional, it goes both ways, from the processor to the Main Memory

Control Bus

This contains the command and control signals from the components

This is bidirectional, it goes both ways, from processor and Memory

The op-code, such as LDA is an mnemonic for what needs to happen

It is a symbolic representation of the binary code

It has a 1-1 relationship with the actual processor

For the exam, the following commands must be known:

• ADD
• SUB
• STO
• LDA
• BRA
• BRZ
• BRP
• INP
• OUT
• HLT
• DAT

Decoder

Logic that "decodes" the op codes from memory

This could be seen similar to a lookup table

Status Register

Contains the status of the processor

Contains the flags

Can be checked by the processor at any point

Clock

Generates pulses at a constant rate

Measured in hz, Hertz

Usually, the faster the clock, the faster things get done

Interrupt Register

Contains the interrupt signals from the components

Checked by the CPU to see if an interrupt has been requested

Cache

Small, fast memory that stores frequently used data

Comes in three levels:

• L1: fastest, but most expensive cache
• L2: slower than l1, but more, and less expensive
• L3: slowest but still fast, cheapest cache